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I'm trying to generate a clean 11.289MHz clock signal from the General Purpose clock, GPCLK0 on GPIO4. The suggested route is to use the 19.2MHz crystal as the source, which seems to work for lower frequencies but no matter what I try it default to 2.5KHz. Reading the docs it seems to imply the that PPL sources should be used.

Does anyone have any further information on what the mentioned sources are particularly:

  • 4 = PLLA per
  • 5 = PLLC per
  • 6 = PLLD per

See page 107 - Clock Control Register of the BCM2835 Peripheral Documentation.

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Did you solve the problem? I would like to generate too a clock signal (between 2-10 MHz), because i would like to read data from shift registers. But i can't make it work. How can i set up the GPCLK0 on GPIO4 pin for a clock signal output? Thanks! –  user3171 Nov 5 '12 at 12:02

1 Answer 1

up vote 2 down vote accepted

Although it is not specified explicitly, I assumed from the spec that:

  • PLLA = 650 MHz
  • PLLB = 400 MHz
  • PLLC = 200 MHz

From this, I would suggest the following:

SRC = 4 (PLLA), MASH = 1, DIVI = 57, DIVF = 592

If I am reading the specs right, this will produce:

min freq = 11.207 MHz, max freq = 11.404 MHz, avg freq = 11.289 MHz

You can try MASH as 2 and 3 experimentally if those work better. You can also try the slower PLL clocks, although accuracy will probably slightly suffer. This is also mentioned in the documentation:

In applications where jitter is a concern, the fastest available clock source should be used.

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