I need to interface device using specific synchronous protocol that requires clock signal within 1..2MHz. Period instability shouldn't exceed 10%. Also, in certain condition protocol requres clock signal to be set into still high level. The whole circuit has two channels that act the same way (so I need to clock signals, etc.).
Can I use RPi to generate the signal accurate enough? RPi have only one PWM channel, but I need two of them. GPIO bitbang looks like solution, but usleep(1) shows ugly performance. It seems this could be solved by creating a driver (OMG!), or using some kernel tweak like Xenomai. But could I really reach accurate delay of 1us or even up to 500ns?
The other solution to me is to use external hardware clock generator, and perform interrupts-based data exchange. Can I reach desired performance at userspace?