Here is some code which uses my pigpiopigpio library to monitor the data and clocks.
It assumes you are using standard shift register signal levels.
Three values are printed per latch.
- the number of bits
- the data assuming most significant bit first format
- the data assuming least significant bit first format
#!/usr/bin/env python
# shiftIn.py
# 2016-03-27
# Public Domain
import time
import pigpio # http://abyz.come.uk/rpi/pigpio/python.html
DATA=23
DATACLK=24
RCLK=25
bit = 0
val = 0
nbits = 0
def cbf(g, l, t):
global bit, val, nbits
if g == DATA:
bit = l
elif g == DATACLK:
nbits += 1
val <<= 1
val |= bit
elif g == RCLK:
val2 = 0
for i in range(nbits):
if val & (1<<i):
val2 |= (1<<(nbits-i-1))
print(nbits, val, val2)
nbits = 0
val = 0
pi = pigpio.pi()
if not pi.connected:
exit(0)
cb1 = pi.callback(DATA, pigpio.EITHER_EDGE, cbf)
cb2 = pi.callback(DATACLK, pigpio.RISING_EDGE, cbf)
cb3 = pi.callback(RCLK, pigpio.FALLING_EDGE, cbf)
time.sleep(600)
cb1.cancel()
cb2.cancel()
cb3.cancel()
pi.stop()