I couldn't find any answer about this by googling.

Here my output of /proc/interrupts:

pi@raspberrypi:~ $ cat /proc/interrupts 
17:       3380  ARMCTRL-level   1 Edge      2000b880.mailbox
18:         36  ARMCTRL-level   2 Edge      VCHIQ doorbell
27:     120102  ARMCTRL-level  35 Edge      timer
40:          0  ARMCTRL-level  48 Edge      bcm2708_fb DMA
42:       9594  ARMCTRL-level  50 Edge      DMA IRQ
44:          0  ARMCTRL-level  52 Edge      DMA IRQ
45:          0  ARMCTRL-level  53 Edge      DMA IRQ
53:          0  ARMCTRL-level  61 Edge      20215080.spi
56:    3568399  ARMCTRL-level  64 Edge      dwc_otg, dwc_otg_pcd, dwc_otg_hcd:usb1
77:       3648  ARMCTRL-level  85 Edge      20804000.i2c
78:          0  ARMCTRL-level  86 Edge      20204000.spi
80:       3800  ARMCTRL-level  88 Edge      mmc0
81:          4  ARMCTRL-level  89 Edge      uart-pl011
FIQ:              usb_fiq
Err:          0

My question is: what is the meaning of the numbers on the 4th column? (1, 2, 35, 48...).

Some information about my system.

pi@raspberrypi:~ $ uname -a
Linux raspberrypi 4.19.66+ #1253 Thu Aug 15 11:37:30 BST 2019 armv6l GNU/Linux

pi@raspberrypi:~ $ cat /proc/cpuinfo 
processor       : 0
model name      : ARMv6-compatible processor rev 7 (v6l)
BogoMIPS        : 697.95
Features        : half thumb fastmult vfp edsp java tls 
CPU implementer : 0x41
CPU architecture: 7
CPU variant     : 0x0
CPU part        : 0xb76
CPU revision    : 7

Hardware        : BCM2835
Revision        : 0013
Serial          : 00000000be0130ff
  • Sounds like the channel of the interrupt controller. May I ask what are you planning to do with this information? Nov 26 '19 at 15:39
  • serverfault.com/questions/896551/…
    – goldilocks
    Nov 26 '19 at 16:05
  • @goldilocks I'm sorry but the link you sent doesn't provide an answer to the question. I had seen this already.
    – nickagian
    Nov 26 '19 at 19:48
  • 1
    nicagain: It was not intended as an answer, which is why it was not posted as an answer (please take the tour to understand better how the site works). I realize that explanation may not jibe with your output. However, since this is something you are already aware of, you might want to refer to this explicitly because it is without doubt very relevant. Another $0.02: You may want to include the LKML in your research.
    – goldilocks
    Nov 26 '19 at 20:50
  • 1
    @goldilocks I have used the site a lot (in other groups though). Anyway, thank you for the hint. You are right, it could be that I hadn't seen that discussion.
    – nickagian
    Nov 26 '19 at 20:57

To the best of my knowledge, when you write software dealing with the interrupts, the IRQ number you will handle always comes from the first column. That's what the CPU is seeing.

The 4th column reveals some details about the interrupt controller, and as you have seen, its format is very platform-dependent. A complex SoC may have more interrupt sources than the CPU supports (for instance, most pins can generate interrupts), so the job of the interrupt controller is to establish a mapping between such sources that are actually in use and the IRQs.

Personally, I would not try to parse the 4th column at all and trust the 5th column instead. E.g. if the interrupt channel 89/Edge is called uart-pl011, I would expect it to be an UART interrupt. So, I needed to deal with UART, I would have to service IRQ 81, listed in the first column on the same line.

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