I'm aware of several different constraints on the Pi5 (and beyond), and I was hoping someone could give the full list and what specifically prevents such a feature (and why).

The next Rpi will still want to keep the same footprint as the previous ones, and the designers also won't want to remove features to include a coprocessor socket (they would remove features possibly to include more sophisticated substitutes... USB4 instead of USB2 maybe).

They want to keep the cost down (though how far down is unclear).

And any new features would have to have some use case for their primary goal, I think (low cost educational computers).

On top of that, there would be wattage concerns as well, if any potential use required that it was more than 15 watts (less?), that'd scuttle the idea too.

Finally, they'll certainly want to use some ARM core or another (for that matter, even a Broadcom fabbed one, I should think).

How do these (and the other constraints I might have missed) make such a feature unviable? Consider that a coprocessor probably needs at minimum 250-300 pins for any reasonable use, and I can't find anything anywhere that uses less than a square inch of space for that. The cost for the socket alone will be significant (but I can't even guess what at their volume). There are only a few candidates for a coprocessor anyway (perhaps an FPGA, or a some older x86 core die-shrunk down really low).

I know this is a dumb idea, but I'd like to know in detail all the reasons that it is dumb.

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    What's the question? – Ingo May 9 at 11:19
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    @tlfong01 The GPU is indeed a coprocessor, but I would be talking about a third one. Instead of being built-in, this one would only be available via a socket (perhaps on the underside of the board). It looks like a P6 core shrunk down to to 10nm could easily fit in a package that's only a half-inch square, and would see a reduction in wattage and a clock freq boost besides. But if it were a socket, it could also be an FPGA or a second GPU, it wouldn't need to be a single option. – John O May 13 at 1:49
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    @tlfong01 I'm not aware of any HATs with any powerful processor. It's just going through the gpio is it not? What sort of bandwidth could that hope to provide? – John O May 13 at 2:32
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    Well, Rpi's 40 pin GPIO connector is actually for communication (SPI I2C etc), the processing is of course on the HAT. Just a cheapie example: US$30 AI HAT for Micky Mouse Projects: (1) "Grove AI HAT for Edge Computing SKU 102991187 - SeeedStudio US$29": seeedstudio.com/Grove-AI-HAT-for-Edge-Computing-p-4026.html. Cheers. – tlfong01 May 13 at 3:39
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    As I said, RPi 40 pin connector is only for Micky Mouse toy projects. Industrial guys might use mini PCIe interface. With mini PCIe, you can DIY your own little HAT, embedding "coprocessors" you like: (2) "Quectel Mini PCIe Module:: quectel.com/product/eg25gminipcIe.htm, (3) "Murata and Google team to develop world’s smallest AI module with Coral intelligence 06/04/2020": murata.com/en-eu/products/info/other/other/2020/0106. Cheers. – tlfong01 May 13 at 3:51

This is NOT possible in any way.

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  • This isn't even an answer. If it is indeed impossible, please explain why instead of just saying "it's not possible". – John O May 13 at 1:46
  • Because there's no way to access any of the processor bus signals you'd need to add any form of co-processor (and if you don't understand that you don't understand what a co-processor does). You've got 27 GPIO, one (or two on RPi4) HDMI, four USB, one ethernet and analog audio interfaces. How would you use those for a co-processor. Frankly, your question is pure nonsense that's asking for something impossible. – Dougie May 13 at 23:06

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