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I'm programming the in- and outputs of a 4x4 matrix keypad for the RPi in order to print the pushed key's value (a letter).

In order to (first) read which row was pushed, the tutorial tells me to convert the row pins to input with a pull up resistance and the column pins to output low. When a key/button is pressed on the pad, a row pin will read a low value.

In order to then read the columns, the "found" row is converted to output high, and the column pins to input with a pull down resistance. When a key/button is pressed on the pad, a column pin will read a high value.

I then asked myself why a pull up was preferred for reading the pushed row, but couldn't make sense out of it. I re-programmed the rows to read for a high value (column pins set to output high) and it worked just as well and made more sense to me (in both reading of row and column: read for a high value).

Why not convert rows to input pull down (instead of pull up) and columns to output high (instead of low)? Wouldn't that make more sense?

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  • Well, the EE guys always prefer pullup to pulldown, for a reason (Google is happy to tell why!). So MCU and most logic circuits make it easy to entertain pullup designs. For example Rpi has built in pull up in their GPIO buffers.You may also easily find typical pull up design keypads, such as in this Q&A: "How can Rpi use a matrix key pad to read multiple, up to 256 keys / buttons?": raspberrypi.stackexchange.com/questions/96259/…. Anyway, pull down is bad taste. Cheers.
    – tlfong01
    Commented May 18, 2020 at 12:18
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    Peter's accepted anser is solid. I believe that one effect of this design is that only one GPIO is high at a time. I don't believe that raising two GPIO at the same time matters at all. Raising all the GPIO simultaneously should work.
    – Chad Farmer
    Commented May 27, 2020 at 20:24

1 Answer 1

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In general the reason electronic engineers prefer pull-ups to pull-downs is that in silicon N type (NPN bipolar or N-channel FET) transistors are better than P type transistors (PNP bipolar or P channel FET).

This meant that when ICs were built out of 1 type of transistor they were built out of N transistors and as a result they were much better at pulling lines low than they were at pulling them high.

With modern CMOS it doesn't matter much, P devices are still intrinsically worse than N ones, but IC manufacturers now use both types of device and compensate by using different geometries for the P devices than the N ones but the habit of using pull-ups rather than pull-downs remains and "open drain" outpus still nearly always drive low.

P.S. your post describes a rather unusual method of reading a matrix.

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    Genius! Thanks! Regarding the method for reading: it looks like you're right, most other tutorials advocate another method. I'll try my best to understand this other one.
    – ola_bandola
    Commented May 18, 2020 at 17:37
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    This is a reasonable answer, but you've added some fallacies: For example, "engineer preferences" only reflect consequences of the laws of physics; e.g. "donor conductivity vs acceptor conductivity"; ref. Also, pull-up vs. pull-down is typically dictated by circumstances; e.g. when using a 2-in NOR gate as an inverter, would you pull up the unused input, or pull it down?
    – Seamus
    Commented May 19, 2020 at 0:15
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    There is a similar long story in this forum, some six years ago: "GPIO: Why wire button to ground rather than +3.3v? - Asked 2013 Viewed 15k times": raspberrypi.stackexchange.com/questions/9481/….
    – tlfong01
    Commented May 21, 2020 at 2:40

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