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are there any public requirements (which I have not found) specifing power supply ramps / gradients

e.g. is there a spec like from 0 to 5V in 5ms or faster

also when turning of, is there any requirement how fast to go from 5 to 0V or can we have a ramp down e.g. when discharging a buffer capacitor?

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The Arm processor requires that reset is kept low until the power is stable. I suspect that the Pis honor that requirement.

For power-down, the ARM says:

6.3.2 Power-Off Sequence

The power supplies can be powered-off in any order as long as LVCMOS supplies operated at 3.3V (DVDD3318_A, DVDD3318_B, or DVDD3318_C) never exceed static 1.8V supplies by more than 2 volts. There is no specific required voltage ramp down rate for any of the supplies (except as required to meet the above mentioned voltage condition).

So the main processor should not be a problem. You may want to investigate for the specific memory card that you use.

Note that the diagrams for the Pi are available at https://www.raspberrypi.org/documentation/hardware/raspberrypi/schematics/README.md. You can see the additional power circuitry there (f.e. the processor runs of 3.3V, not 5V)

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  • Well I expect the PI hardware to handle that. In industrial devices I work with, we have hard requirements with slow ramps and such. The intend of my question is more like if the external 5V supply has special constraints which e.g. a external supply need to comply with, or if the Pi is hardend enougth to cope with e.g. slow rise and fall times – schnedan Oct 9 at 18:04
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There are no such documented requirements.

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The only requirements on 5V supply is that it is within 5% and can supply sufficient current.

The SOC DOES NOT use 5V but a number of lower voltages. These have sequencing requirements but this is handled by the PMIC.

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