What is the raspberry pi pico maximum SPI frequency? I wwould like to know the theoretical maximum given no overclocking and the maximum that is stable,
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well, theoretical and stable max are of course not the same. It also depends on the device, eg ADC max sps might range from 20k to much higher than pico can handle.– tlfong01Oct 20, 2021 at 0:55
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Considering that each chip will behave differently when overclocked, there is no single answer to this.– Dmitry GrigoryevOct 20, 2021 at 6:35
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Unanswerable question.– joanOct 20, 2021 at 8:42
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datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf Look under §4.4.3.4.– prashOct 23, 2021 at 6:38
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2 Answers
As already answered, the maximum clock speed is 62.5MHz.
But there is something else to be aware of. By default, SPI is in the Motorola mode which toggles the chip select pin after each data word. Here is the diagram from section 4.4.3.10 of the datasheet (the commonly used SPI mode: SPO=0, SPH=0):
As you can see, after each word there is a gap of 1.5 clock cycles so that the SSPFSSOUT pin can toggle. That's unfortunate, as it reduces the effective SPI speed by about 16%.
I was trying to drive a ST7789 display, which doesn't need this signal so it's basically wasted. But because the ST7789 samples on the rising edge, SPI mode 3 (SPO=1, SPH=1) can also be used, which looks like this:
As you can see, in this mode the gap is only half a clock tick (the Q signal). That means there is only 6% overhead, which is a lot less. Still not ideal, but it does save a lot of overhead.
Some more notes to get good performance:
- Use DMA. I was using regular register writes, and for some reason it was slower than DMA even though it should have saturated the FIFO.
- You could try using 16-bit words instead of 8-bit words to reduce the overhead by half. You'll probably need to swap bytes though and it may complicate things.
- Apparently it's possible to avoid this gap altogether by using PIO (see the
pio/st7789_lcdexample). I haven't tested this myself.
(This post is here for anyone else trying to speed things up. I've spend hours to figure this all out and I hope it'll be helpful to someone).
Theoretical value, via Prash's comment, on page 526 of the RP2040 datasheet:
4.4.3.4. Clock ratios
… at the maximum SSPCLK (clk_peri) frequency on RP2040 of 133 MHz, the maximum peak bit rate in [controller] mode is 62.5 Mbps
(emphasis/redaction mine)
Practical value? Unanswerable without knowing the electrical characteristics of your setup. Breadboards and jumper wires get noisy above a few MHz. The governing factor is mostly the speed of your SPI peripheral, too.
