I’ve noticed that if measure the rise time of GPIO on a CM3+L in a carrier board, I get very different results. GPIO22 for example, manages <2ns, which seems inline with the electrical specification. But GPIO34 barely manages 12ns.
This is after controlling for parasitic capacitance, trace impedance and measurement error.
I see from http://www.mosaic-industries.com/embedded-systems/microcontroller-projects/raspberry-pi/gpio-pin-electrical-specifications that drive strength is controlled by enabling parallel drivers. But I don’t know if:
- This is specific to certain versions of the Pi.
- Whether this is under software control.
- Whether the pin mode limits/dictates the options. Is there some auto bandwidth control going on or something?