I've become curious about what PCIe is capable of, primarily because the raspberry pi CM4 exposes a "1-lane PCIe" interface into the CPU.
The 1-lane PCIe Gen 2 interface in Broadcom BCM2711 processor is exposed in Raspberry Pi CM4 ...
I'm struggling to find clear definitions of what this is and is not capable of:
- I see from the link above that 1 lane can be split out to multiple other PCIe devices. I presume this goes via some form of hub (I'm imagining something like a USB hub).
- Besides performance constraints, is there a limit on how many ways this splits?
- I'm unclear on whether PCIe is based on a master/slave concept or if it's somehow peer-to-peer.
- Assuming it's master/slave is it possible for the for the CM4 to act as either of these or it somehow hardwired to be the master? IE can a CM4 act as a PCIe peripheral?
- Does "1 lane" infer some sort of performance bottleneck when interacting with a single device? Would a single device typically only connect to one lane?