I've become curious about what PCIe is capable of, primarily because the raspberry pi CM4 exposes a "1-lane PCIe" interface into the CPU.

Example reference here https://www.cnx-software.com/2022/02/07/add-four-pcie-x1-slots-to-raspberry-pi-cm4-io-with-waveshare-pcie-packet-switch-4p-board/:

The 1-lane PCIe Gen 2 interface in Broadcom BCM2711 processor is exposed in Raspberry Pi CM4 ...

I'm struggling to find clear definitions of what this is and is not capable of:

  • I see from the link above that 1 lane can be split out to multiple other PCIe devices. I presume this goes via some form of hub (I'm imagining something like a USB hub).
    • Besides performance constraints, is there a limit on how many ways this splits?
  • I'm unclear on whether PCIe is based on a master/slave concept or if it's somehow peer-to-peer.
    • Assuming it's master/slave is it possible for the for the CM4 to act as either of these or it somehow hardwired to be the master? IE can a CM4 act as a PCIe peripheral?
  • Does "1 lane" infer some sort of performance bottleneck when interacting with a single device? Would a single device typically only connect to one lane?

1 Answer 1


It's pretty simple: https://www.cgdirector.com/guide-to-pcie-lanes/.

All it means is that the Pi CM is an "x1" device, as opposed to "x8", "x16", etc., which is are likely familiar if you've ever installed a PCIe device; motherboards generally offer a number of PCIe slots with a greater number of lanes that can be divided between them in sets, so, eg., if you use slot A in x16 mode, you may not be able to use slot B at all, or you could use both of them in x8 mode. These settings are done through the BIOS.

Each lane is a set of two wires/traces leading to the CPU. An x1 device requires only 1 lane (and cannot accept more).

I'm unclear on whether PCIe is based on a master/slave concept or if it's somehow peer-to-peer.

It is primarily a master-slave relation although some PCIe devices are capable of P2P communication.

PCIe peer-to-peer communication (P2P) is a PCIe feature which enables two PCIe devices to directly transfer data between each other without using host RAM as a temporary storage.

(from https://xilinx.github.io/XRT/master/html/p2p.html)

I'd presume this does not include any Pi CM models.

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