There are many references to a maximum limit of 50mA when sourcing power from the two 3.3V power pins on the GPIO (just for clarity, I am NOT referring to the I/O pins). However, I suspect this current limitation applies to the RPi boards which pre-date the B+ (summer 2014) and used the legacy LDO VR. I believe this limitation no longer applies to the higher capacity RPi models which use the buck converters.

In this excellent review of the B+ power supply by AdaFruit prepared back in July 2014 ( https://learn.adafruit.com/introducing-the-raspberry-pi-model-b-plus-plus-differences-vs-model-b/power-supply ), she indicates the 3.3V power rail is supplied by the RT8020 converter chip which is rated at 1A (key point). Recall that the external power to the B+ is a 5V 2A micro-USB adapter which supports the entire board, including the 5V power rail that supplies USB ports, HDMI, etc. Based on the rating of the RT8020 chip, only 1A of this total 2A is potentially available to the 3.3V power rail.

In this case, the 3.3V power pins should be able to supply any remaining current capacity after essential power consumers like the SOC and GPIO I/O channels draw their power needs which are <= 3.3V. Just as an example, let's say the B+ board is running without any connected USB or peripheral devices (that would normally be the 5V consumers) and the board is consuming 600mA. In this case, the 3.3V power pins on the GPIO should be able to supply up to 400mA. This is a far cry from the meagre 50mA that is so often and mistakenly cited!

Please comment if you agree, or not?

  • 1st Case Reference here: raspberrypi.org/forums/viewtopic.php?t=90390&p=634795 – PhilM Mar 12 '16 at 5:43
  • 2nd Case Reference here: raspberrypi.org/forums/viewtopic.php?f=44&t=51078 – PhilM Mar 12 '16 at 5:44
  • Agree. See answer. I think everybody knows about this. – PNDA Mar 12 '16 at 7:03
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    The question would be more interesting if you could contemplate a way to demonstrate the veracity of what seems more like a claim than a question. It is commonplace and easy to believe we have all the variables in place and everything all figured down with a technical question only to find out we did not, so the quick way to test that is to devise an experiment, for which you'd I'd guess need a small ammeter amongst other things. Otherwise you are just asking people to say, "Sure, makes sense to me to" like a bunch of guys looking under – goldilocks Mar 12 '16 at 9:47
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    an open hood and going, "Right, yeah". It doesn't mean they are wrong, but it is very hard to say if it means much of anything. For example, in joan's other answer she mentions this 1 A being split with the 1V8 rail which is I guess the processor and the memory? What else? What could all that consume at surge? Under what conditions could that occur? – goldilocks Mar 12 '16 at 9:47

The GPIO header isn't entirely made out of GPIO pins.

What you're referring to are only the power pins on the so-called GPIO header. They're almost directly connected to the power rails so it's true they can provide the remaining allowed current. I even powered another Pi using those pins.

The GPIO pins themselves which are connected directly to the SoC are limited to 50mA.

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    Yes, indeed the limit of 50ma is well known for the GPIO I/O pins (totaled across all of them). And the availability of remaining current is also well known for the 5v power pins. But the max current on the 3.3v power pins is commonly mis-stated as having a 50ma limit, which is not true and the point I am making. Further, the max current from the 3.3v power rails is not a fixed value, it's a "remaining allowed" amount as you stated above. – PhilM Mar 12 '16 at 8:28
  • @PhilM So do you have a good example of "the meager 50 ma that is so often and mistakenly cited" WRT the 3.3V power? I'm not disagreeing as I think I've seen that too but I am not positive (I am also pretty sure I've drawn more than that because I just plain don't believe it is that low). – goldilocks Mar 12 '16 at 9:59
  • Examples are in the case reference links I provided above. If you read a lot of other forums and blogs on this topic, you will also find that some folks have implemented a voltage converter to step down the power from the 5v power pin to 3.3v to support attached devices just because they are concerned they may reach/exceed the supposed 50ma limit on the 3.3v power pins. – PhilM Mar 12 '16 at 18:59
  • I don't understand. How is the 3.3V rail separate than the GPIO rail? How can they have different current limits? Don't GPIO pins get power directly from the 3.3V rail? – Bassinator Nov 7 '18 at 16:41
  • @Bassinator GPIO pins, the ones you can use in-code, are connected directly to the SoC, which is sensitive and can't really supply current (rather, they're signal pins, voltage high/low). The 3.3V power pins (pin 1 and 17) are not fed by the SoC, but are connected to the 3.3V power rail itself (which also supplies the SoC, giving you a hint of their current capacity). – PNDA Nov 7 '18 at 16:58

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