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Are there any 5-bit to 32 Port Chips, that would operate:

Converting from 5-bit: inputs: 5 bit address 1 bit value 1 bit clock outputs: 32x 1 bit value (outputs toggled)

Converting to 5-bit: inputs: 32x 1 bit value 5 bit address 1 bit clock outputs: 1 bit value

These would be two separate chips entirely, then each has a 7-bit bus to the GPIO on the RPi (perhaps only 2 wide, and a common clock, address as the program that will be using them will probably only be running on one thread. This could also allow for a much larger data bus, say 15-bit which would give 10 additional i/o's possibly further multiplexed on their own for more ports, or high accuracy DAC/ADCs), so a python program with an abstraction layer on top of GPIO would be able to interact with the real world with 32-inputs, and 32-outputs.

Are there any chips available that would this, or would I have to custom build something?

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  • UUhm, tricky piece of text! What do you want to do, you want to have 32 Input and 32 Output (in one 'databus' style setting) pins and also do some external addressing ??(output) Because if that is the case and speeds is not the highest prio, then using I2C extenders (or ADC for that matter) is the most easy way to go, SPI if you need higher speeds... Or I really do not understand what you want.. – ikku Jan 20 '13 at 15:56
  • Nope, two separate chips, one for input/decoding, and one for output/encoding, but they would both have common elements, such as the clock, and the port selection, which would then either read or write (depending in the chip) from/to the selected port (in 5-bit format) into/from the value 1-bit pin. For the outputs, that would toggle that port to on/off depending on the value, and the input would return 1/0 depending if the selected output is high – topherg Jan 20 '13 at 16:05
  • But the purpose it to do I/O with 32 bit devices? Clock, port selection (aka addressing), read/write signals, sounds like a bus system to me.. And I suppose it needs to buffer because you'll need multiple 5 bit read cycles to read the total 32 bit from the inputs. Sort of a simplyfied ISA bus for RPi, that's the idea? – ikku Jan 20 '13 at 16:49
  • It would be about querying, either select or update, on a defined address, but the selects are will go through one chip, and update will go through another (that bit is simple, its just a selection, perhaps an extra register bit so the system can query its own status) – topherg Jan 20 '13 at 18:00
  • I suppose you checked already the usual sources for ICs with this functionality. I don't think stock TTL (74xx series for example) have something like this, but then again I do not know the whole series of whatever is made from my head. Why don't you try if our neighbor has some good solution: electronics.stackexchange.com, over there there are people who know the whole 74xx series from their head :-). Otherwise FPGA would do the job, but that is extra programming.. – ikku Jan 20 '13 at 18:27
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This is called multiplexing and demultiplexing.

For example, this demux allows you to select one of 16 input with 4 bits of address.

For the multiplexing you describe, you need both a multiplexer (to select a given bit) and D-type flip-flops (to record the state of each bit).

So, for 16 bits, you can get it done with only 3 circuits. There might be circuits for 32 bits, but that would require a lot of pins, especially for the flip-flop, which needs 3 pins per bit, and it's not very common among logic IC.

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  • Initially I was thinking in the same direction, but he also wants clock signal (might be a candidate for the /OE pin).. And the addressing the question is talking about, what is done with that? (I assumed that needs to come from those same 5 GPIO pins) So there needs to be something that separates the addressing cycle from the data cycle. In short I still don't have a clear picture of what is exactly needed. – ikku Jan 21 '13 at 19:40
  • Thats exactly what it is, but the addition of the clock is mainly so the system, perhaps a second ic, will set the data on the output pin, only on the rising edge of the clock signal. So, as the clock goes high, the value pin (high or low) will be set to the pin defined by the 5/6/...-bit address, or for the input on the rising edge of the clock signal, whatever value is on the address (as defined above) is then output onto the value pin. I'm sure they would have to be two different sets of ICs, but with a common address, clock, and bus selector and a value in, and value out, that would do it – topherg Jan 21 '13 at 20:59

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