22

What SPI frequencies does Raspberry Pi support?

Additionally:

  • Are they all supported by the bootc.net SPI driver?
  • Are there any additinal things I should be cautious about when trying to communicate with some other chip via SPI?
21

The Raspberry Pi SPI runs at APB clock speed, which is equivalent to core clock speed, 250 MHz. This can be divided by any even number from 2 to 65536 for the desired speed. The datasheet specifies that the divisor must be a power of two, but this is incorrect. Odd numbers are rounded down, and 0 (or 1) is equivalent to 65536. A divisor smaller than 2 is therefore impossible.

This makes the frequency range be from 3.814 kHz to 125 MHz, with 32768 steps in between.

(There has been a lot of misinformation on this matter, but these results have been verified by experimentation. Please spread the word.)

  • 1
    I think this answer ought to be at the top. – Jon Watte Jan 9 '13 at 18:40
  • Are you sure about this? Gordon asserts that, while you can feed it any even number, only powers of two actually make a difference: Understanding SPI on the Raspberry Pi | Gordons Projects – scruss Feb 2 '13 at 16:45
  • 3
    I tested this with an oscilloscope. I think the problem with Gordon is that he uses the kernel driver, which mangles the clock speed, instead of directly commanding the processor without using the kernel driver. – Nakedible Feb 4 '13 at 14:39
  • 2
    This Forum-Thread provides further information to prove Nakedible's answer: raspberrypi.org/phpBB3/… – Nippey Sep 16 '13 at 13:55
5

The SPI can be run at the core clock speed or divided down for slower peripherals. The core clock is 250 MHz. The divider can be set to any power of two - from 2^0 all the way up to 2^16. This means that SPI frequencies from 3.8 kHz to 250 MHz are supported.

Sources:

  • 1
    Maybe - Farhad is sourcing from datasheets for BCM2835 which is the actual SoC for RPi while my reference is for the BCM2708 which is only part of the SoC. The sources might converge ... but then again they might not. So I think it's better to preserve alternate sources for now. – Maria Zverina Jun 28 '12 at 9:39
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    Oh and area51 lists us as having 1.7 answers per question and states "2.5 answers per question is good, only 1 answer per question needs some work. In a healthy site, questions receive multiple answers and the best answer is voted to the top." :-) – Maria Zverina Jun 28 '12 at 9:41
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    Incorrect answer: 2^0 is not supported, and the divider does not need to be a power of two. – Nakedible Nov 1 '12 at 12:48
  • 1
    @Nakedible can you provide source for your statements? – Maria Zverina Nov 1 '12 at 16:27
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    The bcm2835 datasheet confirms the 2^0 point. raspberrypi.org/wp-content/uploads/2012/02/… This is also confirmed by defines in the bcm2835 library. open.com.au/mikem/bcm2835 As for the non power of two divisors, the datasheet errata mentions that possibly multiple of 2 was meant. elinux.org/BCM2835_datasheet_errata This was also posted on some forum that any multiple of 2 seems to work. All of this has also been confirmed by testing the SPI output on real hardware. See my answer below which specifies this exactly. – Nakedible Nov 1 '12 at 18:01
4

The datasheet of BCM2835 says the following on page 120: The value of the clock register of the SPI block contains.

BC Clock Divider SCLK = Core Clock / CDIV If CDIV is set to 0, the divisor is 65536. The divisor must be a power of 2. Odd numbers rounded down. The maximum SPI clock rate is of the APB clock.

I can't find any reference to what is the maximum frequency of the APB bus, I think that is part of the ARM11 documentation and not this SoC.

  • 1
    Thanks for the reference; I believe the page is 156? CDIV seems to be 16b wide, so goes from 1 to 65536. "Core clock" is probably the 700MHz? So we'd get range from ~10.7kHz up to the mysterious APB limit? – akavel Jun 25 '12 at 21:48
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    You are very welcome, but I am afraid this clock is not the core clock. It is the APB bus: "APB is designed for low bandwidth control accesses, for example register interfaces on system peripherals. This bus has an address and data phase similar to AHB, but a much reduced, low complexity signal list (for example no bursts). It has to support 32bit and 66MHz signals." – FarhadA Jun 25 '12 at 21:54
4

I have tested with the as seen on http://www.brianhensley.net/2012/07/getting-spi-working-on-raspberry-pi.html and changed the speed.

The maximum speed when the test passed is 15MHz = 15000KHz: See result:

spi mode: 0
bits per word: 8
max speed: 15000000 Hz (15000 KHz)

FF FF FF FF FF FF
40 00 00 00 00 95
FF FF FF FF FF FF
FF FF FF FF FF FF
FF FF FF FF FF FF
DE AD BE EF BA AD
F0 0D

The test at 16MHz failed. André

  • 1
    Mine ran ok at 32MHz = 32,000KHz. I've seen it mentioned here that this is the practical limit too. I am running the latest RPi firmware on Raspbian hard float if that makes a difference. – dodgy_coder Aug 27 '13 at 6:01
  • Having RPi 3 running that test at 60MHz successfully. – Vlad Aug 22 '19 at 14:57
1

BC Clock Divider SCLK = Core Clock / CDIV If CDIV is set to 0, the divisor is 65536. The divisor must be a power of 2. Odd numbers rounded down. .....

Linguistically, 'Odd numbers rounded down' is consistent with 'power' being a typo for 'multiple' If it was intended to be a power of two, there would be no need to reference odd numbers.

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