What SPI frequencies does Raspberry Pi support?
- Are they all supported by the bootc.net SPI driver?
- Are there any additinal things I should be cautious about when trying to communicate with some other chip via SPI?
The Raspberry Pi SPI runs at APB clock speed, which is equivalent to core clock speed, 250 MHz. This can be divided by any even number from 2 to 65536 for the desired speed. The datasheet specifies that the divisor must be a power of two, but this is incorrect. Odd numbers are rounded down, and 0 (or 1) is equivalent to 65536. A divisor smaller than 2 is therefore impossible.
This makes the frequency range be from 3.814 kHz to 125 MHz, with 32768 steps in between.
(There has been a lot of misinformation on this matter, but these results have been verified by experimentation. Please spread the word.)
The SPI can be run at the core clock speed or divided down for slower peripherals. The core clock is 250 MHz. The divider can be set to any power of two - from 2^0 all the way up to 2^16. This means that SPI frequencies from 3.8 kHz to 250 MHz are supported.
.rate = 250000000, /* 250MHz */https://github.com/bootc/linux/blob/073993b3f3e23fb8d376f9e159eee410968e0c57/arch/arm/mach-bcm2708/bcm2708.c
The datasheet of BCM2835 says the following on page 120: The value of the clock register of the SPI block contains.
BC Clock Divider SCLK = Core Clock / CDIV If CDIV is set to 0, the divisor is 65536. The divisor must be a power of 2. Odd numbers rounded down. The maximum SPI clock rate is of the APB clock.
I can't find any reference to what is the maximum frequency of the APB bus, I think that is part of the ARM11 documentation and not this SoC.
I have tested with the as seen on http://www.brianhensley.net/2012/07/getting-spi-working-on-raspberry-pi.html and changed the speed.
The maximum speed when the test passed is 15MHz = 15000KHz: See result:
spi mode: 0 bits per word: 8 max speed: 15000000 Hz (15000 KHz) FF FF FF FF FF FF 40 00 00 00 00 95 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF DE AD BE EF BA AD F0 0D
The test at 16MHz failed. André
BC Clock Divider SCLK = Core Clock / CDIV If CDIV is set to 0, the divisor is 65536. The divisor must be a power of 2. Odd numbers rounded down. .....
Linguistically, 'Odd numbers rounded down' is consistent with 'power' being a typo for 'multiple' If it was intended to be a power of two, there would be no need to reference odd numbers.