In the datasheet, the maximum clock frequency (when the ADC is powered with maximum voltage of 5V) is 3.6 MHz. Each read takes about 24 clock cycles which gives us a maximum sampling rate of about 150 KSPS. However, I have a couple of questions:
1) Why is it that the ADC is advertised to be a 200 ksps ADC when the theoretical maximum is about 150 KSPS?
2) Is the calculation that I have done correct?