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I read about SPI(Serial Peripheral Interface) protocol and try to understand their pin functionalities. Where i read about SCLK pin, which is provide serial clock to synchronize the master and slave communication.

So, I have a query regarding to SCLK pin. What does mean by "serial clock to synchronize the master and slave"?

Does it send at the same data rate on both sides like in UART?

Thanks in advance.

  • Read about D flip flops and registers - you'll suddenly understand what SPI is all about – slebetman Aug 30 '17 at 12:40
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It looks you don't know what "clock" means. A clock is something that synchronizes. Say you are supposed to arrive at work at 9 o'clock. When your boss' clock reaches 9 o'clock, he will check if you are absent and flag you as arriving late if so. When your clock reaches 9 o'clock, you check if you have arrived and bang your head against the wall if not.

In electronics, the clocks is usually a binary signal. Anything that uses the clock just watches if it's 1 or 0. An edge (the signal changing from 0 to 1 or vice versa) will be (hopefully) seen by all users of the clock at the same time. In the going to work case, you can change the clock to something that outputs 1 only when it's 9 o'clock to 17 o'clock, and you and your boss will act the same.

Back to SPI. SPI has different modes, I'll be using mode 1 in this example. The master provides a clock that changes periodically. On a rising edge, the master changes MOSI to the next bit in the buffer and the slave changes MISO to the next bit in the buffer. On a falling edge, the master reads MISO into the buffer and the slave reads MISO into the buffer.

Does it send at the same data rate on both sides like in UART? Only the master controls the clock. The slave acts according to the clock. Because the master and the slave read on the same clock edge and write on the same clock edge, data is sent at the same rate in SPI.

Now you've mentioned UART. As you may know, "A" in "UART" stands for "asynchronous". It doesn't have a line dedicated for clock. The two sides synchronize by using their own clock running at the same frequency.

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A SPI bus has usually the following signals

  • SCLK, The clock signal, driven by the master
  • CS, Chip select (CS) or slave select (SS), driven by the master, usually active-low and used to select the slave (since it is possible to connect multiple slave on the same bus).
  • MOSI, Master Out Slave In, driven by the master, the data for the slave will appear on this line.
  • MISO, Master In Slave Out, driven by the slave, where the data from the slave will go to the master.

On a synchronous bus like the SPI, the slave does not sample (does not take into account) it's inputs unless the clock (in this case SCLK) signal has an edge.

The clock phase and polarity (whether the default clock state is low or high, or whether rising or falling-edge are in use) can be defined by the SPI mode.

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    I will add this to the CS explanation: Chip select (CS) or slave select (SS) – MatsK Aug 30 '17 at 9:36

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