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At page 96 of the Manual for the BCM2835, the synopsis for the "GPIO Event Detect Status Registers (GPEDSn)" states that "The bit is cleared by writing a “1” to the relevant bit."

However, regarding the table, an "1" shows that an event is detected, and "0" that this is not the case. Thus, is seems to be unlikely (but not impossible) that writing "1" resets an event. It this a documentation mistake? (It is not listed in BCM2835 datasheet errata.)

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The values read/written to that peripheral address are under the control of the GPIO peripheral firmware.

The firmware knows the difference between a read and a write and will perform the appropriate actions.

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You're right, it does seem illogical, although it is quite common in this scenario. Remember that you're not actually writing to memory - just the register that's mapped to that address.

Although for an avr, there's a pretty good explanation here

In order to make extra sure any pending interrupt gets cleared before re-activating global interrupts (e.g. an external edge-triggered one), it can be necessary to explicitly clear the respective hardware interrupt bit by software. This is usually done by writing a logical 1 into this bit position. This seems to be illogical at first, the bit position already carries a logical 1 when reading it, so why does writing a logical 1 to it clear the interrupt bit?

The solution is simple: writing a logical 1 to it requires only a single OUT instruction, and it is clear that only this single interrupt request bit will be cleared. There is no need to perform a read-modify-write cycle (like, an SBI instruction), since all bits in these control registers are interrupt bits, and writing a logical 0 to the remaining bits (as it is done by the simple OUT instruction) will not alter them, so there is no risk of any race condition that might accidentally clear another interrupt request bit.

You'll find similar explanations by googling

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