I'm using the hardware PWM that is described on page 138 of the BCM2835-ARM-Peripherals document.
The description of the
DMAC-register (page 145) indicates that one can set the FIFO-threshold at which the
PANIC-signal is sent to the Direct Memory Access hardware.
Bits 7:0 specify the DMA Threshold for the
DREQ signal and bits 15:8 the DMA Threshold for the
PANIC signal, so there are 8 bits for each threshold. The default value is
0x7, but there is no description on what this value actually means:
0x7 could indicate 7 free spaces or 7 filled spaces. The FIFO has a size of 8 32bit words, so it also could be the bitmask
0b0000 0111 and indicate either 3 free spaces or 3 filled spaces.
How to use this register so the signals are sent at the proper fifo thresholds?
writel(0x80000E0E, chip->base + PWM_REG_DMAC);
so it sets both thresholds to
- This Raspberry-Pi-DMA-Example sets both thresholds to
PWM_FIFO_SIZE) with the comment:
DREQ is activated at queue < PWM_FIFO_SIZE
- This "PiFM"-Implementation uses
0xFfor both thresholds with the comment:
I think this means it requests as soon as there is one free slot in the FIFO which is what we want as burst DMA would mess up our timing..
- This other "Raspberry PI FM Transmitter" just keeps the default
0x07for both thresholds.
Has someone real knowledge about this or an idea for an experiment one could do to find out what it actually means?