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I know that Raspberry Pi has two Chip Select(CS) pins CE0 and CE1 in its header. However when I look to GPIO pinout. I see that BCM 19,20,21 pins are related to second SPI bus.

Is there really a second SPI bus usable?

Is sharing MISO,MOSI,SCLK lines and seperating CS lines for per SPI slave proper way to connect multiple SPI slaves?

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2 Answers 2

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Though there are 2 hardware SPI busses available, the support for the second spidev is more limited. For instance, the wiringPi library does not support /dev/spidev1.0.

Also, the kernel does not support mode 1 and 3 right now for /dev/spidev1.0. I needed to switch my planned SPI1 device to SPI0 to work around this limitation. In the datasheet I was unable to find an explanation why the driver for the second spi bus is different than for the first.

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    From a hardware point of view the main SPI and auxiliary SPI devices are different. The auxiliary SPI is a much simpler device.
    – joan
    Oct 25, 2017 at 9:16
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    I see, the datasheet raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf gives indeed a difference between the spi0 and the spi1 and spi2 devices.
    – steviethecat
    Oct 25, 2017 at 9:28
  • @steviethecat The documentation seems to imply the opposite, Starting on page 20, the two peripherals are presented as being identical and the register definitions match. It must be a kernel limitation or oversight because it is a thorough implementation that even supports different modes even for read/write (which I have had to use for devices). There is, however a different between the aux/mini UART and the primary UART. The mini is disabled by default and shares an interrupt with the SPI, which may limit the driver somehow, but there is no hardware reason for this.
    – crasic
    Oct 26, 2017 at 1:14
  • @crasic Page 20 documents the auxiliary SPI devices (one of which is available from the Pis with a 40 pin expansion header). The main SPI device is documented on page 148.
    – joan
    Oct 26, 2017 at 7:24
  • @joan good catch. However, in either case both peripheral types support CPOL and CPHA modes, so it is surprising to me that the limitation exists.
    – crasic
    Oct 26, 2017 at 15:47
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Yes, there are two sets of SPI hardware and two SPI buses available from the Pis with the 40 pin expansion header.

See diagram at http://abyz.me.uk/rpi/pigpio/#Type_3

Yes, a separate slave select per slave with the other signals in common is correct.

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  • There are electrical limitations on the maximum number, but in principle its even ok to use a seperate GPIO for an additional CS, it requires keeping track of this in user space which can be error prone and requires locks, but it is supported through device tree if you want to customize this in kernel. SPI is push-pull so its much more tolerant to large fanout compared to I2C and SWI
    – crasic
    Oct 26, 2017 at 1:20

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