I am trying to build a remote control for a jacuzzi using RPI. For that I have been analysing the data between the display and the main board. I found that the display holds 2 shift registers 74HC595 that are daisy chained. Checking what is being sent with a log analyser shows sequences sending 16 bits every time: enter image description here

I did some analysis and I now have a reasonable understanding of what the bit sequences mean so I now need to monitor that so that I can send the information to the app that I will use to do the remote control.

To monitor the data being sent I tried to use code from an earlier post which does show me data but not in line with what I see on the log analyser. Instead of the 16 bits every time I get something like:

(0, 0, 0) (9, 62, 248) (1, 1, 1) (8, 55, 236) (15, 32639, 32639) (9, 407, 467) (16, 65279, 65407) (13, 6159, 7683) (1, 1, 1) (12, 1447, 3674) (13, 8159, 8063) (16, 65277, 49023) (16, 32511, 65406) (1, 1, 1) (2, 3, 3) (16, 65271, 61311) (5, 31, 31) (9, 255, 510) (15, 16126, 16318)

I wonder if the RPI is too fast, too slow or something else is off with the code that prevents me from reading the same values. I am stuck now so I would appreciate any suggestions.

Just to make sure, the code used is:

#!/usr/bin/env python

# shiftIn.py
# 2016-03-27
# Public Domain

import time

import pigpio # http://abyz.me.uk/rpi/pigpio/python.html


bit = 0
val = 0
nbits = 0

def cbf(g, l, t):
   global bit, val, nbits
   if g == DATA:
      bit = l
   elif g == DATACLK:
      nbits += 1
      val <<= 1
      val |= bit
   elif g == RCLK:
      val2 = 0
      for i in range(nbits):
         if val & (1<<i):
            val2 |= (1<<(nbits-i-1))
      print(nbits, val, val2)
      nbits = 0
      val = 0

pi = pigpio.pi()

if not pi.connected:

cb1 = pi.callback(DATA, pigpio.EITHER_EDGE, cbf)
cb2 = pi.callback(DATACLK, pigpio.RISING_EDGE, cbf)
cb3 = pi.callback(RCLK, pigpio.FALLING_EDGE, cbf)




Problem resolved by changing settings:

Looking at the logic analyser shows data high when inactive; means we need to change the initial setting of bit=0 to bit=1 to prevent misinterpreting the first bit on clock signal when that bit is a '1'.

The clock is also high when inactive. That means first clock pulse needs to be measured on falling edge instead of rising edge.

The script 'processes' the byte when latch (RCLK) ends. As latch is high when inactive I needed to trigger that on rising edge instead of falling edge.

Making those changes put the results fully in line with the logic analyser.


By default pigpio samples at 200kHz. That means frequencies of 100kHz and below should be seen reliably.

If you can you need to slow the data rate to something which can be reliably captured by pigpio.

You can start the daemon so that it samples at a higher rate by using the s option.

Perhaps try -s 2.


  • Thanks for the quick response! Starting the daemon with -s 2 made I big change in that I now always see 16 bits coming in as expected. Weird thing is that the values are still not in line with the logic analyser; the 65407 value is there every alternate set but I don't recognise the other values:
    – Smittyman
    Jun 15 '18 at 11:49

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