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I'm building a project using the MCP3914 8-channel analog front end (ie ADC) device connected to the Raspberry Pi's SPI peripheral.

The device has a continuous read mode where you request the value of one register then hold the CS low and it cycles through all of the registers, transmitting the value of each one, for as long as you hold CS low. I'd like to use this mode to continuously sample the values sampled by the ADC. Ideally, the transfer should be done with DMA, to keep CPU utilisation low. The SPI peripheral could write data into a circular buffer with the userspace either keeping up or losing data if it doesn't read it in time, or it could perhaps write to two buffers, passing each to a userspace program when it fills up and then switching to the other.

What are my options for implementing this? It looks like the spidev driver doesn't support reading more than about 4k from the device (1 page?). Also the documentation here points to a github project for DMA-enabled SPI, but the wiki for that project says that mainline now has DMA capability, with a link to the driver source code. So how do we do SPI DMA with the spidev driver on modern kernels?

Assuming that I can't use the spidev driver, I guess I'm stuck using the bcm2835 library to manipulate the peripheral directly. I don't know a lot about this - not even if it's going to be in user space or kernel space.

Can someone give (or point me to) some advice please?

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I believe the current Linux /dev/spidevx.y driver for the Pi supports DMA. I believe it automatically uses DMA if the transfer is over a certain size (below this size the overhead of setting up DMA does not save time).

I am afraid I know of no documentation other than the driver source code (available on github).

I am fairly sure it does not support buffering for continuous reads.

I'm sorry this is so vague but I have never looked at this in detail.

If the bits per second transferred is less than 500kbps you might be able to set up your own cyclic buffer (using a technique used to read multiple ADCs simultaneously).

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