3

I want to toggle an GPIO pin with a certain accuracy. (i.e. latency about 1 us). I have a Raspberry Pi 3 model.

Therefore I wrote a simple test kernel module. The toggling loop does basically this:

     spin_lock_irqsave(&my_lock, flags);
   while(count)
   {
       volatile int k;
       iowrite32(16, (u8*)gpio+0x1c);
       for(k=0;k< 10;k++);
       iowrite32(16, (u8*)gpio+0x28);
       for(k=0;k< 10;k++);
       count--;
   }
   spin_unlock_irqrestore(&my_lock, flags);

I monitor the pin with an oscilloscope and trigger for gaps. Here I can see that every few seconds I get latency gaps up to 5us.

My question is: Where do those gaps come from?

My understanding was that the spin lock disables IRQs for the core my driver is running. And therefore I have assumed to have the whole CPU core for my driver all the time.

Update 2018/08/20: I verified that spin_lock_irqsave disables IRQ but not FIQ. Does Linux/Raspberry use FIQ interrupts?

2

Even though you are using Linux you might be better off asking at the raspberrypi.org baremetal forum. They are probably more aware of potential glitches.

I know of two potential glitch sources.

  1. Every second or so the dynamic RAM refresh rate is recalculated. This will add a glitch of about 5µs or so. However according to this issue that behaviour was fixed so should no longer be a problem.
  2. The GPIO are accessed off the AXI bus. If the bus is busy for other reasons this may also cause a glitch.

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