I am reverse-engineering a late-'80s IBM Wheelwriter typewriter, which runs off of an Intel 8088. It has a ROM chip, specifically: https://www.datasheets360.com/pdf/1277907997291200345?xrefPartId=1277907997291200345&alternatePartManufacturerId=0

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in a socket that holds the X86 code, and I'd like to emulate that chip by responding to memory requests via my Raspberry Pi, through the GPIO pins.

I am concerned that I won't be able to read the 14 address pins and respond on the 8 data pins fast enough. Here is the timing data:

enter image description here

Before I go and build the circuit, is this something that will be doable? What other things should I measure? Based on my logic analyzer readings, it looks like the pulse width coming from the 8088 is about 120ns.

  • No way, not as a drop-in. This may be functionally possible with a baremetal single thread application with no linux, but for that purposes there are other MCU's and an Arduino may be the best hobby board approach. In industry this type of emulation is done with FPGA. Electrically your 8088 may hate both anyway but you would have have to deal with 5V logic issue if you try with PI
    – crasic
    Jun 4, 2019 at 18:06
  • @crasic Thanks! Would an Arduino be faster? I will look at FPGA options, or I will just get an EEPROM and figure out some other tools to do the reverse-engineering. Jun 4, 2019 at 18:11
  • That might not be the best idea... Related: raspberrypi.stackexchange.com/a/87865/19949 concerning the speed
    – Ghanima
    Jun 4, 2019 at 18:12
  • Faster is not the right word, architecture wise you will have an easier time determining if it is feasible as you are in baremetal regime. You are emulating a 5mhz ROM , the challenge isn't processor time or memory access time but servicing IO interrupt and response within the very tight timing requirements of a memory bus. It is possible to do baremetal RPI or write a custom kernel driver, but even with an RTOS the io latency up and down the kernel stack is too much for a memory bus
    – crasic
    Jun 4, 2019 at 18:15
  • 2
    @Ghanima BCM has a mode to drive GPIO directly from clock, but even then the limit is 100MHz with 1.25V io, it will be slower with 3.3V io and any load but 10MHz is likely close to real limit . The software toggle baremetal rate should be comparable if PLL is configured. A good related answer is this one on ee.se electronics.stackexchange.com/a/388074/1729
    – crasic
    Jun 4, 2019 at 18:20

1 Answer 1


If I had to do this, I would use a 100ns 62256 SRAM chip and added some dual-port logic made from six 74244/74245 chips to it.

Then, I would use an additional µC, e.g. an ATtiny85 or such and clock it with the 4.77 MHz 8088 clock, so the RAM could be accessed by both CPUs in an alternating fashion. The RAM port is flipped with the 8088 clock, too. That way, the RAM is transparent to both.

I connected the ATtiny to the Pi via I²C, UART or USB, whatever fits best.

The simpler alternative is using a ZIF socket, a 29F256 Flash ROM and a programmer for it.

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