I'm creating a project in C++ on a raspberry pi zero and C on PIC18F26Q10 where multiple PICs will transmit sensor data to the raspberry pi. Both devices can send and receive data to and from each other. My issue is that the raspberry Pi which will be the PRX device is only able to receive data on Datapipe 0 and 1. Sending data to any other datapipe results in a max retry interrupt on the PIC side. I'm able to transmit succesfully on all datapipe addresses to the PIC, however the PICs have only datapipe 0 and auto ack for datapipe 0 enabled. I've enabled all datapipes in the EN_RXADDR register and also enabled auto ack for all datapipes in the EN_AA_REG register.
Am I missing a setting or detail to enable datapipes 2 through 5.
I'm using C++ and the PIGPIO library to control the GPIO.
My datapipe adresses in defined in the header file as:
char channelP0[5] = { 0xE7, 0xE7, 0xE7, 0xE7, 0xE7 };
char channelP1[5] = { 0xC2, 0xC2, 0xC2, 0xC2, 0xC2 };
char channelP2[5] = { 0xC2, 0xC2, 0xC2, 0xC2, 0xC3 };
char channelP3[5] = { 0xC2, 0xC2, 0xC2, 0xC2, 0xC4 };
char channelP4[5] = { 0xC2, 0xC2, 0xC2, 0xC2, 0xC5 };
char channelP5[5] = { 0xC2, 0xC2, 0xC2, 0xC2, 0xC6 };
The above code block is identical for both the PIC18F26Q10 and the RAspberry pi.
Here is my initialize code:
int NRF24L10::Initialize(int channel)
{
if (handle < 0) //If already open, ignore and return -1.
{
gpioWrite(NRF24_CE, 0);
handle = spiOpen(channel, 100000, 0);
WriteRegister(CONFIG_REG, 0x0D); // RX, TX & Max Retry interrupt enabled, PRX mode, Power Down, 2 byte CRC
WriteRegister(EN_RXADDR_REG, 0x3F); // Enable all data pipe RX addresses
WriteRegister(EN_AA_REG, 0x3F); // Enable auto acknowledge for all data pipes
Powerup();
WriteRegister(SETUP_AW_REG, 0x03);
WriteRegister(SETUP_RETR_REG,0xF3 );
WriteRegister(SETUP_AW_REG, 0x03);
WriteRegister(SETUP_RETR_REG, 0xF3);
WriteRegister(RF_CH_REG, 0x50); // Set to 2480Mhz, outer edge of chanel 13 but still within legal limits
WriteRegister(RF_SETUP_REG, 0x02); // Set gain low for testing.
WriteRegister(STATUS_REG, 0x70);
Activate(); // Enable R_RX_PL_WID
WriteRegister(DYNPD_REG, 0x3F); // Enable dynamic data width on all datapipes
WriteRegister(FEATURE_REG, 0x04); // Enable dynamic data width feature
WriteRegisterBytes(RX_ADDR_P0_REG, channelP0, 5);
WriteRegisterBytes(RX_ADDR_P1_REG, channelP1, 5);
WriteRegister(RX_ADDR_P2_REG, channelP2[4]);
WriteRegister(RX_ADDR_P3_REG, channelP3[4]);
WriteRegister(RX_ADDR_P4_REG, channelP4[4]);
WriteRegister(RX_ADDR_P5_REG, channelP5[4]);
FlushRX();
FlushTX();
PRXmode();
return handle;
}
else
{
return -1;
}
}