1

There are 2 clock sources that are not officially (?) listed with a string id available to the vcgencmd measure_clock command.

# for i in {0..255}; do vcgencmd measure_clock $i; done | grep -v "=0"

frequency(1)=400000000
frequency(9)=163683000
frequency(22)=47999000
frequency(26)=4800000
frequency(28)=299999000
frequency(29)=148500000
frequency(42)=300000000
frequency(43)=300000000
frequency(45)=1200000000
frequency(47)=200000000
frequency(50)=1920000

# for src in arm core h264 isp v3d uart pwm emmc pixel vec hdmi dpi ; do x=$(vcgencmd measure_clock $src ); echo -e "$src:\t$x"; done;

arm:    frequency(45)=1200000000
core:   frequency(1)=400000000
h264:   frequency(28)=300000000
isp:    frequency(42)=300000000
v3d:    frequency(43)=300000000
uart:   frequency(22)=48000000
pwm:    frequency(25)=0
emmc:   frequency(47)=200000000
pixel:  frequency(29)=148500000
vec:    frequency(10)=0
hdmi:   frequency(9)=163683000
dpi:    frequency(4)=0

There are (at least) 2 clocks here that are non-zero, 26 and 50, but which do not have an official name.

What do they represent? (Are there others?)

  • 1
    they seem to correspond to /sys/kernel/debug/clk/otp/clk_rate and /sys/kernel/debug/clk/tsens/clk_rate – Jaromanda X May 6 '18 at 1:10
0

Thanks to @Jaromanda's answer.

  • clk #26 = otp - is the One Time Programmable clock rate
  • clk #50 = tsens - is the temperature sensor clock rate

In the linux kernel file: clk-bcm2835.c:

    /*
     * Clock for the temperature sensor.
     * Generally run at 2Mhz, max 5Mhz.
     */
    [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK(
        .name = "tsens",
        .ctl_reg = CM_TSENSCTL,
        .div_reg = CM_TSENSDIV,
        .int_bits = 5,
        .frac_bits = 0),
...
    /* One Time Programmable Memory clock.  Maximum 10Mhz. */
    [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK(
        .name = "otp",
        .ctl_reg = CM_OTPCTL,
        .div_reg = CM_OTPDIV,
        .int_bits = 4,
        .frac_bits = 0,
        .tcnt_mux = 6),

We can also find all clocks from the sysfs kernel debug path:

#  sudo cat /sys/kernel/debug/clk/clk_summary

   clock                         enable_cnt  prepare_cnt        rate   accuracy   phase
----------------------------------------------------------------------------------------
 uart1_pclk                               0            0   125000000          0 0
 uart0_pclk                               0            0     3000000          0 0
 apb_pclk                                 0            0   126000000          0 0
 otg                                      0            0   480000000          0 0
 osc                                      7            7    19200000          0 0
    gp2                                   1            1       32768          0 0
    tsens                                 1            1     1920000          0 0
    vec                                   0            0    19200000          0 0
    otp                                   0            0     4800000          0 0
    timer                                 0            0     1000002          0 0
    pllh                                  4            4  1485000000          0 0
       pllh_pix_prediv                    1            1  1485000000          0 0
          pllh_pix                        0            0   148500000          0 0
       pllh_aux                           1            1     5800782          0 0
       pllh_rcal_prediv                   1            1     5800782          0 0
          pllh_rcal                       0            0      580078          0 0
    plld                                  3            3  2000000024          0 0
       plld_dsi1                          0            0     7812501          0 0
       plld_dsi0                          0            0     7812501          0 0
       plld_per                           3            3   500000006          0 0
          gp1                             1            1    25000000          0 0
          hsm                             0            0   163682866          0 0
          uart                            1            2    47999625          0 0
       plld_core                          2            2   500000006          0 0
          sdram                           0            0   166666668          0 0
    pllc                                  3            3  2000000024          0 0
       pllc_per                           1            1  1000000012          0 0
          emmc                            0            0   200000002          0 0
       pllc_core2                         0            0     7812501          0 0
       pllc_core1                         0            0     7812501          0 0
       pllc_core0                         2            2  1000000012          0 0
          vpu                             1            1   400000000          0 0
             aux_spi2                     0            0   400000000          0 0
             aux_spi1                     0            0   400000000          0 0
             aux_uart                     0            0   400000000          0 0
             peri_image                   0            0   400000000          0 0
    pllb                                  2            2  1200000000          0 0
       pllb_arm                           1            1   600000000          0 0
    plla                                  2            2  2000000024          0 0
       plla_ccp2                          0            0     7812501          0 0
       plla_dsi0                          0            0     7812501          0 0
       plla_per                           0            0     7812501          0 0
       plla_core                          1            1  1000000012          0 0
          h264                            0            0   250000003          0 0
          isp                             0            0   250000003          0 0
          v3d                             0            0   250000003          0 0
 dsi1p                                    0            0           0          0 0
 dsi0p                                    0            0           0          0 0
 dsi1e                                    0            0           0          0 0
 dsi0e                                    0            0           0          0 0
 cam1                                     0            0           0          0 0
 cam0                                     0            0           0          0 0
 dpi                                      0            0           0          0 0
 tec                                      0            0           0          0 0
 smi                                      0            0           0          0 0
 slim                                     0            0           0          0 0
 gp0                                      0            0           0          0 0
 dft                                      0            0           0          0 0
 aveo                                     0            0           0          0 0
 pcm                                      0            0           0          0 0
 pwm                                      0            0           0          0 0

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.