Are the ARM Mailbox and Doorbell interrupts ever triggered?

Question

I'm writing some very bare metal multi-tasking code that manipulates the hardware on a Pi3.

Part of that is to initialise a frame buffer, and I'd like to avoid polling loops, where possible. (e.g. Waiting for mailbox 0 to contain a message in response to my request.)

I thought the ARM Mailbox interrupt might be triggered by the GPU responding to my message, but nothing happens, as far as I can tell.

It's not important, in the general run of things, but I'd like a consistent approach to communicating with intelligent hardware components.

Answer 1

I found my answer in the QEMU source code, hw/misc/bcm2835_mbox.c. The interrupts have to be enabled in the config register associated with the mailbox, the documentation for which I've not seen or forgotten.

It looks like you enable the not-empty, not-full, and is-empty interrupts using bits 0, 1, and 2, respectively, and can identify the reason for an interrupt by reading the same register, and examining bits 4, 5, and 6. Errors, should you decide to make some, will be reported in bits 8, 9, and 10, and cleared on the next write.

Naturally, the GPU interrupt will have to have been enabled in QA7 (bit 8 in CoreN interrupt source, and routed to the desired core in GPU interrupt routing), and in the bcm2835 periperal's Base Interrupt enable register, bit 1.

#define ARM_MC_IHAVEDATAIRQEN    0x00000001 /* mbox irq enable:  has data */
#define ARM_MC_IHAVESPACEIRQEN   0x00000002 /* mbox irq enable:  has space */
#define ARM_MC_OPPISEMPTYIRQEN   0x00000004 /* mbox irq enable: Opp is empty */
#define ARM_MC_MAIL_CLEAR        0x00000008 /* mbox clear write 1, then  0 */
#define ARM_MC_IHAVEDATAIRQPEND  0x00000010 /* mbox irq pending:  has space */
#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mbox irq pending: Opp is empty */
#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mbox irq pending */
/* Bit 7 is unused */
#define ARM_MC_ERRNOOWN   0x00000100 /* error : none owner read from mailbox */
#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */
#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */