I have a test set-up where an STM32F4 microcontroller is reading in an analogue signal and sending it to a windows PC through UART. The windows PC runs a Python script that interprets the data and saves it in a file system as .CSV. This works fine but the datalogger is limited by the ADC (12bit 2MSPS)on the STM32 and the UART speed (max data transfer seems to be approx. 14kbit/s).

I have access to an FPGA dev kit with an ADC of 14 bit and up to 65MSPS, so I want to use this to read my analogue signal. The difficulty is how to store and organise the resulting signals. My original plan was to use Raspberry Pi 4 as a SPI slave and transfer from the FPGA to the Pi through SPI and use either a python script or a C program to do the same thing as on the windows PC. After some research it is not possible to configure the Pi as a SPI slave (impossible for the pi to know when the analogue signal is captured so it can't be the master) and therefore this isn't an option.

I want to use a raspberry pi 4 to log the data as I can convert the data to .CSV easily and it will be simpler to sort and organise the thousands of files that will be generated. As the FPGA needs to be the "master" in this set-up what options do I have for transferring the generated data to the Pi? Ideally I would like a minimum transfer speed of 10mbit/s but anything faster than 1mbit/s could be considered.

  • IMHO, your question, while interesting, is off-topic for this site. Just as a suggestion, perhaps consider doing some more research, and making a decision wrt what protocols to use, and your overall architecture. The time to ask a question here is after you've determined what role the RPi will play, Wrt protocols & limitations, this article may provide something you can use as a starter?
    – Seamus
    Sep 1 '21 at 10:06
  • (max data transfer seems to be approx. 14kbit/s) -> May or may not be useful (my experience with FPGAs is limited), but: You should be able to implement a UART that's only limited by the chip's clock, eg., a 16 Mhz clock should be enough for 1 *MBytes*/sec (note the Pi's UART probably isn't reliable beyond that point).
    – goldilocks
    Sep 1 '21 at 14:57

the FPGA needs to be the "master" in this set-up

Not really. Consider buffering: when the FPGA gets a new sample from the ADC, it stores it in a FIFO block. At the same time it waits for the Pi to request new data: if the FIFO is empty, it sends a NACK, otherwise it transmits a sample from the FIFO. Obviously, the read requests from the Pi should come more often than the data from the ADC, otherwise the FIFO will overflow at some point.

SPI should be fine for speeds around 10mbit/s, if more bandwidth is necessary I would check out USB cores available for your FPGA.

  • I decided that I could just use a separate GPIO pin to tell the raspberry pi when the data had been captured and to request a transfer.
    – ChrisD91
    Sep 2 '21 at 14:52

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